Working for a leader in power in power electronics, this is a great opportunity to join a growing team, as UVM verification engineer.
Job duties:
1. Developing test plans, tests and verification infrastructure using SV/UVM methodology
2. Building reusable bus functional models, monitors, checkers and scoreboards
3. Performing coverage driven verification closure
4. Performing block level, multi-block level and system-level verification
5. Performing Gate level simulations
6. Performing Mixed Signal simulations
7. Implementing Regression tests
8. Performing Formal Verification
9. Working closely with IC designers and post-silicon engineers
Qualifications and Background
Requirements:
10. Knowledge/experience with HDL (SystemVerilog / Verilog / VHDL), particularly for testbenches creation
11. Knowledge/experience in scripting languages, such as Tcl and Python
12. Some knowledge of ASIC design flow and related verification step
Nice to have:
13. Some experience in digital RTL design
14. Knowledge of UVM environments and classes
15. Some experience with main EDA vendors simulators such as Questasim and Xcelium
16. Knowledge of DFT structures and test pattern generation
17. Some experience in silicon validation/characterisation
18. Experience working on Git.
For more information, please contact Rob Hudson.