The Chips-IT Foundation is expanding its microelectronics design team and is seeking a highly experienced Principal Physical Design Engineer to play a key technical leadership role in advanced System-on-Chic (SoC) development programs. The position will contribute to cutting-edge R&D; activities, working closely with architecture, RTL, verification, and technology teams in a state-of-the-art microelectronics design environment. The Principal Physical Design Engineer will be responsible for leading and executing complex digital design flows for advanced semiconductor nodes. The role requires deep hands‑on expertise across the full physical implementation lifecycle, from netlist handoff through place & route, signoff, and tape‑out, while also providing technical mentorship and driving best practices within the design team. The work can be carried out either in Pavia or in Bologna. Key Responsibilities Lead and execute end‑to‑end physical design flows for complex SoCs and IP blocks, from RTL handoff to GDSII. Collaborate closely with RTL, verification, DFT, and architecture teams to resolve design and implementation issues. Work with PDKs and technology teams to ensure correct usage of advanced-node design rules and constraints. Develop, document, and improve physical design methodologies, scripts, and automation flows. Mentor junior engineers and provide technical leadership across physical design activities. Required Qualifications Master’s degree (or PhD) in Electrical Engineering, Computer Engineering, or a related field. Extensive hands‑on experience in physical design for advanced technology nodes (e.g., 16nm and below). Strong expertise with industry‑standard EDA tools (Cadence, Synopsys, Siemens). Solid understanding of semiconductor fabrication processes and foundry design requirements. Proficiency in Tcl, Python, or Perl for flow automation and methodology development. Experience supporting multiple tape‑outs in advanced nodes