Ph3Senior Engineer - Silicon Physical Design (Italy based) /h3 pApply for the bSenior Engineer - Silicon Physical Design (Italy based) /b role at bAxelera AI /b. /p h3About Us /h3 pAxelera AI is not your regular deep-tech startup. We are creating the next‑generation AI platform to support anyone who wants to help advancing humanity and improve the world around us. In just four years we have raised a total of $120 million and built a world‑class team of 220+ employees (including 49+ PhDs with more than 40 000 citations), both remotely from 17 different countries and with offices in Belgium, France, Switzerland, Italy, the UK, headquartered at the High Tech Campus in Eindhoven, Netherlands. We have also launched our Metis™ AI Platform, which achieves a 3‑5x increase in efficiency and performance, and have visibility into a strong business pipeline exceeding $100 million. Our unwavering commitment to innovation has firmly established us as a global industry pioneer. Are you up for the challenge? /p h3Position Overview /h3 pAs a Senior Silicon Physical Design Engineer at Axelera AI you will play a crucial role in developing cutting‑edge multi‑core in‑memory compute SoCs. Leveraging your expertise in ASIC Physical Design from RTL to GDS, you will be responsible for synthesis, floorplanning, place and route, extraction, timing analysis, physical verification, EMIR sign‑off and formal verification. You will collaborate closely with architecture and RTL teams to ensure successful project execution. /p h3Key Responsibilities /h3 ul liPerform synthesis, floorplanning, place and route, extraction, timing analysis and physical verification. /li liEnsure timing closure, constraint generation and optimisation. /li liExecute clock tree synthesis (CTS) and clock‑building techniques. /li liIntegrate IPs including memories, I/Os, embedded processors, DDR, networking fabrics and analog IPs. /li liUtilise EDA tools such as Primetime, StarRC, Genus, Innovus, Design Compiler, ICC/ICC2, FC and Calibre. /li liDevelop automation scripts in Python, Tcl or Perl. /li liDebug and solve technical challenges related to physical design. /li liCollaborate with architecture, RTL and verification teams. /li /ul h3Qualifications /h3 ul li10+ years of experience in Physical Design (RTL to GDS). /li liStrong communication and teamwork skills. /li liExpertise in synthesis, timing analysis and timing closure. /li liHands‑on experience with leading EDA tools (Primetime, StarRC, Genus, Innovus, Design Compiler, ICC/ICC2, FC, Redhawk and Calibre). /li liProficiency in clocking techniques and CTS. /li liExperience in IP integration across various domains. /li liStrong scripting skills (Python, Tcl or Perl). /li liProven problem‑solving and debugging capabilities. /li liFluent in English (spoken and written). Italian not required. /li /ul h3Highly Preferred /h3 ul liExperience in top‑level integration and I/O ring design. /li liKnowledge of chip‑package‑board co‑simulation and packaging. /li liAbility to influence design methodologies and tool flows. /li liExperience working with EDA vendors to resolve tool issues. /li liUnderstanding of semiconductor device physics and multi‑domain design. /li /ul h3Location /h3 pThis position is based in Italy (hybrid or remote setup). We also support relocation to Bologna, Florence or Milan for talent based abroad that is interested in this role. /p h3What We Offer /h3 pThis is your chance to shape and be part of a dynamic, fast‑growing, international organisation. We offer an attractive compensation package, including a pension plan, extensive employee insurances and the option to get company shares. An open culture that supports creativity and continual innovation is waiting for you. Collaborative ownership and freedom with responsibility characterise the way we act and work as a team. /p h3Equal Opportunity Diversity /h3 pAt Axelera AI we wholeheartedly embrace equal opportunity and hold diversity in the highest regard. Our steadfast commitment is to cultivate a warm and inclusive environment that empowers and celebrates every member of our team. We welcome applicants from all backgrounds to join us in shaping the future of AI. /p h3Seniority Level /h3 ul liMid‑Senior level /li /ul h3Employment Type /h3 ul liFull‑time /li /ul h3Job Function /h3 ul liEngineering and Information Technology /li /ul h3Industry /h3 ul liSemiconductor Manufacturing /li /ul /p #J-18808-Ljbffr