FPGA Signal Processing Engineer (MATLAB to HDL Conversion)
Location: Pisa, Italy
Start Date: ASAP
Overview
We're looking for a Signal Processing Engineer with strong FPGA experience to port advanced algorithms from MATLAB into deployable, hardware-optimized FPGA implementations on Xilinx RFSoC platforms.
Key Responsibilities
Analyze and optimize signal processing algorithms currently developed in MATLAB.
Port and implement these algorithms in HDL (VHDL/Verilog) suitable for FPGA deployment.
Collaborate with software, systems, and FPGA developers to ensure correct functional behavior and integration.
Validate implementations through simulation and on-board testing.
Required Skills
Strong background in digital signal processing (DSP) .
Experience porting algorithms from MATLAB/Simulink to HDL .
Proficiency in HDL (VHDL or Verilog) and Xilinx FPGA development (Vivado) .
Familiarity with fixed-point arithmetic and hardware optimization techniques.
Understanding of FPGA resource constraints and timing closure.
Desirable
Prior use of RFSoC or Zynq Ultrascale+ platforms.
Experience with Simulink HDL Coder or other model-based hardware design tools.
Knowledge of Petalinux or embedded systems.