What you will doFor more than 25 years, imec has been offering an ASIC prototyping and production service to worldwide companies. Imec helps its customers to design their integrated circuits (chips) and bring them from the prototype to the production stage. Our list of customers includes more than 900 universities and companies worldwide. For the further extension of the physical digital implementation group (Back-End group) in DSRD, we are looking for a highly motivated engineer. DSRD, as part of imec, has an extensive industrial experience, contacts with leading industrial foundries, and long-standing relationships with all the main EDA tool vendors and IP providers. This unit supports worldwide customers in the layout, prototype, fabrication and test of advanced electronic products. As Physical ASIC design engineer within DSRD, you will be in direct contact with our customers for future projects. You will have full understanding of the complete Cadence Innovus Place&Route; flow: Set up the flow for the specific library set and foundry node used Set up low power design (UPF) Floorplanning & power grid design Detailed Timing Driven Placement STA & possible design optimisation for setup Clock Tree Synthesis Scan chain re-stitching Detailed Timing Driven Route (incl. SI) IPO's (in-place optimization) to get the timing in all corners correct Solve setup & hold violations Sign-off extraction (SPEF/QUANTUS) Sign-off timing (TEMPUS) Sign-off Power analysis (VOLTUS) Physical verification (DRC, ERC, LVS, ANT) Logic equivalent check For hierarchical designs you can take the lead for partitioning and split the top level SDC file into timing budget requirements/constraints of the sub-blocks. You will work directly with the Physical Design implementation team during the entire chip design cycle to drive signoff closure for tape‐out. You are also the technical voice to the customer to discuss his specifications. What we do for youWe offer you the opportunity to j