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Junior digital design and risc-v architectures engineer (giussago)

Giussago
Fondazione Chips-IT
Pubblicato il 29 aprile
Descrizione

Junior Digital Design and RISC-V Architectures EngineerApply through LinkedInThe position in briefJob title: Junior Digital Design and RISC-V Architectures EngineerWorkplace: Pavia/Bologna, ItalyDeadline: How to apply: Apply through LinkedInAbout Fondazione Chips-ITThe Foundation "Italian Center for the Design of Semiconductor Integrated Circuits," also known as the Chips-IT Foundation, is a nonprofit research and technology organization under the supervision of the Ministries of Industry.The Foundation is Italy's first RTO (Research and Technology Organization) vertically focused on semiconductor research and stands as a center of excellence in frontier research on semiconductor design, as well as a pivotal center of the Italian semiconductor ecosystem and expertise.Missions Of The Foundation

promote the design and development of integrated circuitsstrengthen the system of professional training in the field of microelectronicsensure the establishment of a network of universities, research centers and enterprises that fosters innovation and technology transfer in the field

RoleThe Chips-IT Foundation is seeking Junior Researchers to contribute to cutting-edge research and development initiatives centered on digital design and RISC-V architectures. The project focuses on developing advanced digital processors, accelerators, and custom SoCs based on the RISC-V instruction set architecture (ISA) as well as dedicated accelerators.This role will involve participating in the design, optimization, and verification of high-performance, low-power digital systems for applications in next-generation computing platforms, IoT, and embedded systems. Junior Researchers will have the opportunity to learn and apply novel design methodologies, verification techniques, and hardware-software co-design strategies to support innovation in the RISC-V ecosystem. The work can be carried out either in Pavia or in Bologna.Key Responsibilities

Support research and development activities related to digital designs, including processors, accelerators, and SoCs based on the RISC-V architecture.Assist in the design, implementation, and verification of digital building blocks (Processors, Accelerators, Memory and Communication Subsystems, etc.) for high-performance, low-power systems.Collaborate with senior team members and contribute to technical discussions, design reviews, and documentation.Participate in integration and testing phases on FPGA or silicon platforms.(Optional) Contribute to dissemination activities including technical reports, academic publications, or conference presentations.

Required Qualifications

Master's degree (or close to completion) in Electrical Engineering, Computer Engineering, or a related field with a focus on digital design and processor architectures (Mandatory).Fundamental knowledge of hardware description languages (HDL) such as Verilog or VHDL, and digital design tools for synthesis, simulation, and verification (Mandatory).Basic familiarity with RISC-V architecture and interest in custom extensions or hardware-software co-design.Understanding of FPGA-based prototyping and exposure to ASIC design flows.Eagerness to learn and grow in the fields of digital design and processor architecture.Good analytical, problem-solving, and communication skills.Team spirit and motivation to contribute to innovative research and collaborative projects.

What We Offer

Competitive compensation and contract type, to be negotiated based on qualifications and experiencePossibility to enter into a PhD conjugating your job with a research program that will grant you the PhD title.Lunch ticketsPrivate health care coverage depending on your role and contractStructured growth path, with ongoing access to training and updatesNetworking opportunities with industry-leading professionalsInternational environmentHybrid work policyTax deductions: Candidates from abroad, comprising Italian citizens, who have carried scientific research activity abroad and meet specific requirements, may be entitled to a taxable income deduction up to 90% for a period of 6 to 13 years

Non verrà redatta e pubblicata alcuna graduatoria o elenco degli idonei.La Fondazione Si Riserva La Facoltà Di

prorogare o riaprire il termine di scadenza del presente avviso;revocare il presente avviso;non procedere ad alcuna scelta tra le candidature presentate, ove ritenute non rispondenti alle funzioni di cui al avviso; senza che gli interessati possano avanzare alcuna pretesa o diritto.

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