PWe’re growing! Our team in Parma (Italy) is seeking a Sr. ASIC Design Engineer. /ppbr/ppstrongResponsibilities: /strong /ppbr/pulliDeveloping micro-architecture specifications for a next generation Computer Vision processor; /liliDesigning and implementing Verilog/SytemVerilog modules for cutting edge SOCs. Examples of such modules include: Video compression logic, Image processing logic, Vector processors and Device / Memory controllers; /liliDesign integration, logic synthesis, and design optimization for timing, area and power; /liliDeveloping front-end methodologies and tool flows; /li /ulpbr/ppstrongRequirements: /strong /ppbr/pulliMaster’s degree in Electrical Engineering with 0-4 years of experience; /liliVery good understanding of VLSI/ASIC design, Computer architecture and Logic design; /liliGood knowledge and experience in using hardware description languages (Verilog/SystemVerilog); /liliAbility to program in scripting languages, like Python and Perl; /liliKnowledge of design verification, and functional coverage; /liliStrong communication skills and a good team player; /liliKnowledge of logic synthesis and timing closure is a must; /liliKnowledge and/or experience in the areas of Image/Video processing, computer vision, machine learning are plus; /li /ulpbr/ppbr/ppTo apply, please submit resume with subject: strongJOB#VLSI /strongto or apply online on Ambarella website. /ppbr/ppAs an Equal Opportunity/Affirmative Action Employer, Vislab and Ambarella recruit qualified applicants without regard to race, color, national origin, sex, physical disability, or veteran status. /ppbr/ppPlease find at this link our privacy disclaimer dedicated to candidates data, accordingly to the GDPR: /p