Experteer Overview
In this role you will contribute to the development of high-speed PAM/Coherent DSPs and PHYs by crafting efficient RTL and integrating IPs. You’ll collaborate with architecture, verification, and back-end teams to ensure robust, clocked digital designs that meet timing and functional goals. You will work across the full chip design flow, from RTL to DFT and post-silicon debugging, enabling scalable solutions for cloud data centers and AI networks. This position offers a meaningful opportunity to shape next-generation hardware and work with cross-functional experts.
Retribuzione / Benefits
* Develop RTL using SystemVerilog and back-end resources
* Integrate internal and external vendor IPs
* Design, debug, and support ICs, IPs and block DFT
* Specify and implement chip digital features
* Collaborate with architecture, floorplanning, backend, verification, DFT, STA teams
* Participate in RTL development, DFT, synthesis, static timing, formal verification, CDC, lint, and functional verification
* Develop ASIC specifications and micro-architecture for signal processing and communication algorithms
* Assist design automation of CAD EDA flow
* Develop post-silicon debug and correlation
* Collaborate with cross-functional teams including architects, designers, verification, physical design, and software/firmware engineers
Responsabilità
* MS/PhD in EE or related field (MS preferred)
* Fluent in RTL coding techniques (SystemVerilog)
* Experience with multi-clock designs
* Synthesis, static timing closure, formal verification, gate-level simulations, block-level functional verification
* Test structures for DFT, IP integration, fault models, coverage improvement
* Hands‑on experience across chip development with frontend tools and methodologies
* Able to multi‑task in a fast‑changing environmentTeam player with can‑do attitude and effective communication
* High‑speed (>1 GHz) DSP product design experience desirable
* Knowledge of scripting languages (Python, Perl, Tcl) and UNIX shell desirable
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