Experteer OverviewIn this role you will drive mixed-signal verification for ASICs within the MEMS sGROUP, contributing across the full verification flow from specification to product industrialization. You will work with cross-functional teams to apply cutting-edge verification methodologies at subsystem and SoC levels, shaping robust analog and mixed-signal designs. The position offers exposure to advanced tools, Cadence environments, and diverse projects that advance ST's smart, greener technology. You will thrive by solving complex verification challenges and delivering reliable results that support product readiness.Retribuzione / BenefitsDefinition and development of verification test benchesDevelopment of verification components and test cases for simulationDebugging failures and creating simulation scenarios for various studiesWork with advanced verification methodologies at subsystem and SoC levelsResponsabilitàKnowledge of analog custom circuits (e.g., ADCs, DACs, comparators)Experience with analog, digital and mixed-signal simulation environmentsBugs analysis and reporting and analog SystemVerilog AssertionsModeling languages such as SystemVerilog, Verilog-AMS; analog model definition and validationCoverage concepts and digital logic basicsScripting languages (Python)UPF for mixed-signal simulations (plus)SystemVerilog and UVM knowledge (plus)Cadence-based tools and environments (plus)Communication protocols in mixed simulations (I2C, SPI, I3C)Formal tools for top-level connectivityVersion control systemsFluent English and strong team collaborationRequisiti fondamentali
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