P Engineering; Information Technology; Newly graduated; Research and development /pp Locations: Italia/Modena /pp strongIC VERIFICATION ENGINEER (junior) /strong /ph3 Job Description /h3p We are looking for a junior strongIC Verification Engineer /strong to join our IC team. /pp In your new role you will be responsible for: /pulli Performing Gate-level and mixed-signal simulations /lili Performing block level, multi-block level and system-level verification /lili Working closely with designers and post-silicon validation engineers /li /ulp strongQualifications and Background /strong /pp uRequirements: /u /pulli Basic knowledge of HDL (SystemVerilog / Verilog / VHDL) /lili Good knowledge in scripting languages, such as Tcl and Python /lili Good knowledge of FW development /li /ulp uNice to have: /u /pulli Some experience in digital RTL design is a huge plus /lili Some experience in silicon validation/characterization is a plus. /lili Experience working on Git /lili Hands-on experience on HW design and lab equipment /lili Knowledge of UVM infrastructure /li /ulp strongSoft Skills /strong /pulli Good interpersonal skills /lili Ability to work in a team /lili Organizational skills /lili Results-oriented mindset /li /ulp strongPreferred Experience /strong /pulli MS Degree in Electronics or Computer Science or Physics. /lili Knowledge of English written and verbal (B2 or higher) /li /ulp strongWhat We Offer /strong /pulli Employee fringe benefits (welfare) /lili Dedicated healthcare check-up /lili Annual bonus /lili Friendly working environment within talented team /li /ul #J-18808-Ljbffr