Experteer Overview
In this role you will drive mixed-signal verification for ASICs within the MEMS sGROUP, contributing across the full verification flow from specification to product industrialization. You will work with cross-functional teams to apply cutting-edge verification methodologies at subsystem and SoC levels, shaping robust analog and mixed-signal designs. The position offers exposure to advanced tools, Cadence environments, and diverse projects that advance ST's smart, greener technology. You will thrive by solving complex verification challenges and delivering reliable results that support product readiness.
Retribuzione / Benefits
- Definition and development of verification test benches
- Development of verification components and test cases for simulation
- Debugging failures and creating simulation scenarios for various studies
- Work with advanced verification methodologies at subsystem and SoC levels
Responsabilità
- Knowledge of analog custom circuits (e.g., ADCs, DACs, comparators)
- Experience with analog, digital and mixed-signal simulation environments
- Bugs analysis and reporting and analog SystemVerilog Assertions
- Modeling languages such as SystemVerilog, Verilog-AMS; analog model definition and validation
- Coverage concepts and digital logic basics
- Scripting languages (Python)
- UPF for mixed-signal simulations (plus)
- SystemVerilog and UVM knowledge (plus)
- Cadence-based tools and environments (plus)
- Communication protocols in mixed simulations (I2C, SPI, I3C)
- Formal tools for top-level connectivity
- Version control systems
- Fluent English and strong team collaboration
Requisiti fondamentali
