YOUR ROLEFaccia ora il prossimo passo nella sua carriera: scorra verso il basso per leggere la descrizione completa del ruolo e invii la sua candidatura.The position is aimed at a Mixed Signal verification engineer with previous experience in analog and mixed simulations of ASICs. The candidate will join the Mixed Verification team of MEMS GROUP and will have the opportunity to see the entire ASIC verification process from specification definition to final product industrialisation. Responsibilities include definition and development of verification test benches, development of verification components, test‑case development for simulation, debugging failures, and creating simulation cases for various studies. As an experienced professional, the engineer will work with cutting‑edge verification methodologies on both subsystem and SoC levels.The position is open in both Castelletto (Italy) and Toulouse (France). We are looking for Senior Profiles/Team Leaders.Your Skills & ExperiencesThe ideal candidate has a good knowledge of analog custom circuits (e.g., ADC, DAC, comparators), analog, digital and mixed‑signal simulation environments and tools, bugs analysis and reporting, and analog SystemVerilog assertions.Basic knowledge of modelling languages such as SystemVerilog RNM, Verilog‑AMS, analog model definition and implementation, analog model verification and validation, coverage, digital logic gates, scripting languages like Python, and Unified Power Format (UPF) applied to mixed‑signal simulations is a plus.An additional plus will be knowledge of SystemVerilog and UVM methodology, tools and environments for mixed‑signal simulations (Cadence‑based), communication protocols in mixed simulations (e.g., I2C, SPI and I3C), formal tools for top‑level connectivity, and version control systems.The candidate also has soft skills such as good communication, fluency in English, teamwork, and collaboration across the entire MEMS GROUP Design team.At ST, we ende