PpbPrincipal Physical Digital Design Engineer /b /p pbApply through LinkedIn /b /p pbThe position in brief /b /p pbJob title: /b Principal Physical Digital Design Engineer /p pbWorkplace: /b Pavia/Bologna, Italy /p pbDeadline: /b /p pbHow to apply: /b Apply through LinkedIn /p pThe Foundation “Italian Center for the Design of Semiconductor Integrated Circuits,” also known as the Chips‑IT Foundation, is a non‑profit research and technology organization under the supervision of the Ministries of Industry. The Foundation is Italy’s first RTO (Research and Technology Organization) vertically focused on semiconductor research and stands as a center of excellence in frontier research on semiconductor design, as well as a pivotal center of the Italian semiconductor ecosystem and expertise. /p h3Missions Of The Foundation /h3 ul liPromote the design and development of integrated circuits. /li liStrengthen the system of professional training in the field of microelectronics. /li liEnsure the establishment of a network of universities, research centers and enterprises that fosters innovation and technology transfer in the field. /li /ul h3Role /h3 pThe Chips‑IT Foundation is expanding its microelectronics design team and is seeking a highly experienced Principal Physical Design Engineer to play a key technical leadership role in advanced System‑on‑Chip (SoC) development programs. The position will contribute to cutting‑edge RD activities, working closely with architecture, RTL, verification, and technology teams in a state‑of‑the‑art microelectronics design environment. The Principal Physical Design Engineer will be responsible for leading and executing complex digital design flows for advanced semiconductor nodes. The role requires deep hands‑on expertise across the full physical implementation lifecycle, from netlist handoff through place route, signoff, and tape‑out, while also providing technical mentorship and driving best practices within the design team. The work can be carried out either in Pavia or in Bologna. /p h3Key Responsibilities /h3 ul liLead and execute end‑to‑end physical design flows for complex SoCs and IP blocks, from RTL handoff to GDSII. /li liCollaborate closely with RTL, verification, DFT, and architecture teams to resolve design and implementation issues. /li liWork with PDKs and technology teams to ensure correct usage of advanced‑node design rules and constraints. /li liDevelop, document, and improve physical design methodologies, scripts, and automation flows. /li liMentor junior engineers and provide technical leadership across physical design activities. /li /ul h3Required Qualifications /h3 ul liMaster’s degree (or PhD) in Electrical Engineering, Computer Engineering, or a related field. /li liExtensive hands‑on experience in physical design for advanced technology nodes (e.g., 16 nm and below). /li liStrong expertise with industry‑standard EDA tools (Cadence, Synopsys, Siemens). /li liSolid understanding of semiconductor fabrication processes and foundry design requirements. /li liProficiency in Tcl, Python, or Perl for flow automation and methodology development. /li liExperience supporting multiple tape‑outs in advanced nodes. /li /ul h3What We Offer /h3 ul liCompetitive compensation and contract type, to be negotiated based on qualifications and experience. /li liPossibility to enter into a PhD conjugating your job with a research program that will grant you the PhD title. /li liLunch tickets. /li liPrivate health care coverage depending on your role and contract. /li liStructured growth path, with ongoing access to training and updates. /li liNetworking opportunities with industry‑leading professionals. /li liInternational environment. /li liHybrid work policy. /li liTax deductions: Candidates from abroad, comprising Italian citizens, who have carried scientific research activity abroad and meet specific requirements, may be entitled to a taxable income deduction up to 90 % for a period of 6 to 13 years. /li /ul pNon verrà redatta e pubblicata alcuna graduatoria o elenco degli idonei. /p h3La Fondazione Si Riserva La Facoltà Di /h3 ul liprorogare o riaprire il termine di scadenza del presente avviso; /li lirevocare il presente avviso; /li linon procedere ad alcuna scelta tra le candidature presentate, ove ritenute non rispondenti alle funzioni di cui all’avviso; senza che gli interessati possano avanzare alcuna pretesa o diritto. /li /ul /p #J-18808-Ljbffr