The position is aimed at a Mixed Signal verification engineer with previous experience in analog and mixed simulations of ASICs. The candidate will join the Mixed Verification team of MEMS GROUP and will have the opportunity to see the entire ASIC verification process from specification definition to final product industrialisation. Responsibilities include definition and development of verification test benches, development of verification components, test‑case development for simulation, debugging failures, and creating simulation cases for various studies. As an experienced professional, the engineer will work with cutting‑edge verification methodologies on both subsystem and SoC levels.
The position is open in both Castelletto (Italy) and Toulouse (France). We are looking for Senior Profiles/Team Leaders.
The candidate also has soft skills such as good communication, fluency in English, teamwork, and collaboration across the entire MEMS GROUP Design team.
At ST, we endeavor to foster a diverse and inclusive workplace and we do not tolerate discrimination. We aim to recruit and retain a diverse workforce that reflects the societies around us. We strive for equity in career development, career opportunities, and equal remuneration. We encourage candidates who may not meet every single requirement to apply, as we appreciate diverse perspectives and provide opportunities for growth and learning. xjrgpwk Diversity, equity, and inclusion (DEI) is woven into our company culture.