Job Description and RequirementsSynopsys is seeking a highly motivated and innovative digital verification engineer with exceptional knowledge in verifying high-speed digital designs. The candidate will work as part of an experienced mixed-signal design and verification team, involved in verifying current and next-generation PAM-based SerDes products. This position offers an excellent opportunity to collaborate with skilled digital and mixed-signal engineers responsible for delivering high-end mixed-signal designs from specification development to functional and performance testing on prototype test-chips.Main Responsibilities:Writing modular constrained-random Verilog and SystemVerilog testbenchesPerforming functional coverageAssertion coverage and code coverageCreating and tracking test plansEvaluating failure cases and running gate-level simulationsKey Qualifications:BSEE or MSEE with 10+ years of digital verification experience in the industryHands-on experience in writing complex test cases in Verilog and SystemVerilogFamiliarity with code quality metricsPreferred Experience / KnowledgeHigh-speed digital mixed-signal design verificationAsynchronous clock domain crossingFamiliarity with UVM methodology and verification using VCS/VerdiGood organization and communication skillsAt Synopsys, we’re at the heart of innovations like self-driving cars, Artificial Intelligence, the cloud, 5G, and the Internet of Things. We power these breakthroughs with advanced chip design and software security technologies. If you share our passion for innovation, we want to meet you.Our Silicon IP business focuses on integrating more capabilities into SoCs quickly. We offer a broad portfolio of silicon IP—pre-designed blocks of logic, memory, interfaces, analog, security, and embedded processors—to help customers meet performance, power, and size requirements, reducing time to market and risk.Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.Job DetailsCategory: EngineeringCountry: ItalySubcategory: ASIC Digital DesignHire Type: EmployeeRequisition Number: 49463BRLocations: Agrate Brianza, Pavia, Italy
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