PpWorking for a leader in power in power electronics, this is a great opportunity to join a growing team, as UVM verification engineer. /p h3Job duties: /h3 ul liDeveloping test plans, tests and verification infrastructure using SV / UVM methodology /li liBuilding reusable bus functional models, monitors, checkers and scoreboards /li liPerforming coverage driven verification closure /li liPerforming block level, multi-block level and system-level verification /li liPerforming Gate level simulations /li liPerforming Mixed Signal simulationsImplementing Regression tests /li liPerforming Formal Verification /li liWorking closely with IC designers and post-silicon engineers /li /ul h3Qualifications and Background /h3 h3Requirements: /h3 ul liKnowledge / experience with HDL (SystemVerilog / Verilog / VHDL), particularly for testbenches creation /li liKnowledge / experience in scripting languages, such as Tcl and Python /li liSome knowledge of ASIC design flow and related verification step /li /ul h3Nice to have: /h3 ul liSome experience in digital RTL design /li liKnowledge of UVM environments and classes /li liSome experience with main EDA vendors simulators such as Questasim and Xcelium /li liKnowledge of DFT structures and test pattern generation /li liSome experience in silicon validation / characterisation /li liExperience working on Git. /li /ul pFor more information, please contact Rob Hudson. /p /p #J-18808-Ljbffr