We are currently searching for a Senior Analog Design Engineer with expertise in designing ICs for the communications market. The employer is a world-class semiconductor company, known for their strong portfolio of IC solutions reaching various markets.
Must-haves
Analog design in the multi-GHz range
Proven experience in designing ICs from architecture definition to lab characterization and volume production.
Ability to work on-site in Pavia, Italy, full-time
Required Skills
Custom layout and EDA CAD tools
IC performance measurement and debugging
Strong communication, presentation, and documentation skills
Proficiency in Italian and English (minimum B2 level)
Preferred or Nice-to-have Skills
Experience with multi-Gbps electrical SerDes or electro-optical transceivers
Knowledge of advanced CMOS nodes, including FinFET
Years of Experience:
12+ years of work experience in IC design, with a focus on analog design and project management.
Industry Experience:
Experience in the semiconductor industry, specifically in designing ICs for communication infrastructure, is required.
Education Requirements:
Master’s degree and/or PhD in Electrical Engineering or related fields.
Compensation:
A competitive compensation package is available. Salary is based on experience level and market data.
Role
The Chips-IT Foundation is seeking an experienced Verification Engineer to support the development and validation of advanced digital IPs and System-on-Chip (SoC) platforms. The role focuses on creating and maintaining verification environments using industry-standard methodologies (e.g., UVM), ensuring functional correctness of designs from specification to tape-out. The position also involves collaboration with design, architecture, and software teams to deliver reliable and high-quality silicon. The work can be carried out either in Pavia or in Bologna.
Key Responsibilities:
Define and implement verification strategies at IP and SoC levels.
Develop and maintain UVM-based verification environments, including testbenches and functional coverage.
Design and execute test plans aligned with design specifications and requirements.
Debug RTL and simulation issues using advanced tools and techniques.
Integrate verification components and ensure complete test coverage.
Contribute to regression infrastructure and manage automated test execution.
Collaborate closely with RTL designers, DFT engineers, and physical implementation teams.
Support post-silicon bring-up and validation activities as needed.
Required Qualifications:
Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
At least 5 years of experience in digital design verification.
Strong knowledge of SystemVerilog and UVM methodology.
Hands-on experience with simulation and debug tools (e.g., QuestaSim, VCS, Verdi).
Familiarity with industry-standard protocols such as AMBA AXI, APB, and AHB.
Experience in writing constrained-random testbenches and analyzing coverage metrics.
Good understanding of digital design, SoC architecture, and RTL development.
Strong teamwork, communication, and documentation skills.
What we offer
Competitive compensation and contract type, to be negotiated based on qualifications and experience
Lunch tickets
Private health care coverage depending on your role and contract
Structured growth path, with ongoing access to training and updates
Networking opportunities with industry-leading professionals
International environment
Tax deductions: Candidates from abroad, comprising Italian citizens, who have carried scientific research activity abroad and meet specific requirements, may be entitled to a taxable income deduction up to 90% for a period of 6 to 13 years
The Foundation “Italian Center for the Design of Semiconductor Integrated Circuits,” also known as the Chips-IT Foundation, is a nonprofit research and technology organization under the supervision of the Ministries of Industry.
The Foundation is Italy's first RTO (Research and Technology Organization) vertically focused on semiconductor research and stands as a center of excellence in frontier research on semiconductor design, as well as a pivotal center of the Italian semiconductor ecosystem and expertise.
Missions of the Foundation:
promote the design and development of integrated circuits
strengthen the system of professional training in the field of microelectronics
ensure the establishment of a network of universities, research centers and enterprises that fosters innovation and technology transfer in the field
Disclaimer
No ranking list or list of suitable candidates will be prepared and published.
The Foundation reserves the right to:
a. extend or reopen the deadline of this notice;
b. revoke this notice;
c. not make any selection from among the applications submitted if they are deemed not to meet the functions set forth in the notice;
without any claims or rights being asserted by the interested parties.
Junior Digital Design and RISC-V Architectures Engineer Role
The Chips-IT Foundation is seeking Junior Researchers to contribute to cutting-edge research and development initiatives centered on digital design and RISC-V architectures. The project focuses on developing advanced digital processors, accelerators, and custom SoCs based on the RISC-V instruction set architecture (ISA) as well as dedicated accelerators.
This role will involve participating in the design, optimization, and verification of high-performance, low-power digital systems for applications in next-generation computing platforms, IoT, and embedded systems. Junior Researchers will have the opportunity to learn and apply novel design methodologies, verification techniques, and hardware-software co-design strategies to support innovation in the RISC-V ecosystem. The work can be carried out either in Pavia or in Bologna.
Key Responsibilities:
Support research and development activities related to digital designs, including processors, accelerators, and SoCs based on the RISC-V architecture.
Assist in the design, implementation, and verification of digital building blocks (Processors, Accelerators, Memory and Communication Subsystems, etc.) for high-performance, low-power systems.
Collaborate with senior team members and contribute to technical discussions, design reviews, and documentation.
Participate in integration and testing phases on FPGA or silicon platforms.
(Optional) Contribute to dissemination activities including technical reports, academic publications, or conference presentations.
Required Qualifications:
Master's degree (or close to completion) in Electrical Engineering, Computer Engineering, or a related field with a focus on digital design and processor architectures (Mandatory).
Fundamental knowledge of hardware description languages (HDL) such as Verilog or VHDL, and digital design tools for synthesis, simulation, and verification (Mandatory).
Basic familiarity with RISC-V architecture and interest in custom extensions or hardware-software co-design.
Understanding of FPGA-based prototyping and exposure to ASIC design flows.
Eagerness to learn and grow in the fields of digital design and processor architecture.
Good analytical, problem-solving, and communication skills.
Team spirit and motivation to contribute to innovative research and collaborative projects.
What we offer
Competitive compensation and contract type, to be negotiated based on qualifications and experience
Lunch tickets
Private health care coverage depending on your role and contract
Structured growth path, with ongoing access to training and updates
Networking opportunities with industry-leading professionals
International environment
Tax deductions: Candidates from abroad, comprising Italian citizens, who have carried scientific research activity abroad and meet specific requirements, may be entitled to a taxable income deduction up to 90% for a period of 6 to 13 years
Senior Digital Design and RISC-V Architecture Engineer Role
The Chips-IT Foundation is seeking Senior Researchers to lead and contribute to cutting-edge research and development initiatives centered on digital design and RISC-V architectures. The project focuses on the development of advanced digital processors, accelerators, and custom SoCs based on the RISC-V instruction set architecture (ISA), as well as domain-specific hardware accelerators.
This role will involve leading the design, optimization, and verification of high-performance, low-power digital systems for next-generation computing platforms, IoT, and embedded applications. Senior Researchers will play a key role in defining design methodologies, driving innovation in hardware-software co-design, and contributing to the advancement of the RISC-V ecosystem at both technical and strategic levels. The work can be carried out either in Pavia or in Bologna.
Key Responsibilities:
Lead research and development activities in digital design, including processors, accelerators, and SoCs based on RISC-V architecture.
Define and guide the architecture, design, implementation, and verification of complex digital subsystems (Processors, Accelerators, Memory and Communication Subsystems, etc.).
Supervise and mentor junior researchers, including Master's and PhD students, across multiple research and development projects.
Develop and disseminate research outcomes through publications in high-impact scientific journals and presentations at leading international conferences.
Drive the adoption of emerging methodologies in digital design, verification, and hardware/software co-design.
Collaborate with industry and academic partners, contributing technical leadership and vision to multi-stakeholder projects.
Support the development of project proposals and strategic R&D; initiatives aligned with national and international funding opportunities.
Required Qualifications:
Master's or Ph.D. degree in Electrical Engineering, Computer Engineering, or a related field with a strong focus on digital design and processor architectures ( Mandatory ).
At least 10 years of experience in digital hardware design, preferably with a mix of academic and industrial exposure.
Deep proficiency in hardware description languages (Verilog, VHDL) and digital design toolchains for synthesis, simulation, and verification ( Mandatory ).
Extensive experience with RISC-V architecture, including custom ISA extensions, microarchitecture design, and hardware-software co-design.
Hands-on experience with tape-outs and chip bring-up in advanced CMOS/FinFET technology nodes (28nm, 16nm, or below).
Proven knowledge in FPGA/ASIC design flows, integration of complex SoCs, and system-level verification.
What we offer
Competitive compensation and contract type, to be negotiated based on qualifications and experience
Lunch tickets
Private health care coverage depending on your role and contract
Structured growth path, with access to training and updates
Networking opportunities with industry-leading professionals
International environment
Tax deductions: Candidates from abroad, comprising Italian citizens, who have carried scientific research activity abroad and meet specific requirements, may be entitled to a taxable income deduction up to 90% for a period of 6 to 13 years
The Foundation “Italian Center for the Design of Semiconductor Integrated Circuits,” also known as the Chips-IT Foundation, is a nonprofit research and technology organization under the supervision of the Ministries of Industry.
The Foundation is Italy's first RTO (Research and Technology Organization) vertically focused on semiconductor research and stands as a center of excellence in frontier research on semiconductor design, as well as a pivotal center of the Italian semiconductor ecosystem and expertise.
Missions of the Foundation:
promote the design and development of integrated circuits
strengthen the system of professional training in the field of microelectronics
ensure the establishment of a network of universities, research centers and enterprises that fosters innovation and technology transfer in the field
Disclaimer
No ranking list or list of suitable candidates will be prepared and published.
The Foundation reserves the right to:
a. extend or reopen the deadline of this notice;
b. revoke this notice;
c. not make any selection from among the applications submitted if they are deemed not to meet the functions set forth in the notice;
without any claims or rights being asserted by the interested parties.
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