Ph3Senior Silicon Physical Design Engineer – Axelera AI /h3 pWe are looking for a Senior Silicon Physical Design Engineer to develop cutting‑edge multi‑core in‑memory compute SoCs. The role covers the entire ASIC physical design flow from RTL to GDS, including synthesis, floorplanning, place and route, extraction, timing analysis, physical verification, EMIR sign‑off, and formal verification. You will collaborate closely with architecture and RTL teams. /p h3Key Responsibilities /h3 ul liPerform synthesis, floorplanning, place and route, extraction, timing analysis, and physical verification. /li liConstraint generation, timing analysis and optimization. /li liExecute clock tree synthesis (CTS) and custom clock‑building techniques. /li liIntegrate IPs including memories, I/Os, embedded processors, DDR, networking fabrics, and analog IPs. /li liUtilize EDA tools such as Primetime, StarRC, Genus, Innovus, Design Compiler, ICC/ICC2, FC, and Calibre. /li liDevelop automation scripts in Python, Tcl, Bash and contribute to flow development. /li liDebug and solve technical challenges related to physical design. /li liCollaborate with architecture, RTL, and verification teams. /li /ul h3Qualifications /h3 ul li10+ years of experience in Physical Design from RTL to GDS. /li liStrong communication and teamwork skills. /li liExpertise in all aspects of physical design. /li liHands‑on experience with leading EDA tools (Primetime, StarRC, Genus, Innovus, Design Compiler, ICC/ICC2, FC, Redhawk, and Calibre). /li liProficiency in clocking techniques and CTS. /li liExperience in IP integration across various domains. /li liStrong scripting skills (Python and Tcl). /li liProven problem‑solving and debugging capabilities. /li liFluent in English (spoken and written). /li /ul h3Highly Preferred /h3 ul liExperience in floorplanning and top‑level integration. /li liKnowledge of chip‑package‑board co‑simulation and packaging. /li liExperience working with EDA vendors to resolve tool issues. /li liUnderstanding of semiconductor device physics and multi‑domain design. /li /ul h3Location /h3 pFlexible working arrangement. Options: /p ul liWork from one of our Axelera AI offices in Leuven (Belgium), Amsterdam or Eindhoven (Netherlands), Florence or Milan (Italy), or Bristol (UK) if you are locally based. /li liWork fully remotely from any European country (including the UK). /li liRelocate with us to Italy (Florence or Milan) or the Netherlands (Amsterdam or Eindhoven). /li /ul pPriority will be given to candidates based in Belgium or Italy. /p h3What We Offer /h3 pAn attractive compensation package, pension plan, extensive employee insurances and company shares. A culture that supports creativity, continual innovation, collaborative ownership and freedom with responsibility. /p h3Equal Opportunity /h3 pAt Axelera AI, we wholeheartedly embrace equal opportunity and hold diversity in the highest regard. We welcome applicants from all backgrounds to join us in shaping the future of AI. /p /p #J-18808-Ljbffr