PWorking for a leader in power in power electronics, this is a great opportunity to join a growing team, as UVM verification engineer. /ppbJob duties : /b /pulliDeveloping test plans, tests and verification infrastructure using SV / UVM methodology /liliBuilding reusable bus functional models, monitors, checkers and scoreboards /liliPerforming block level, multi-block level and system-level verification /liliPerforming Mixed Signal simulations /liliImplementing Regression tests /liliWorking closely with IC designers and post-silicon engineers /li /ulpQualifications and Background /ppbRequirements : /b /pulliKnowledge / experience with HDL (SystemVerilog / Verilog / VHDL), particularly for testbenches creation /liliKnowledge / experience in scripting languages, such as Tcl and Python /liliSome knowledge of ASIC design flow and related verification step /li /ulpbNice to have : /b /pulliKnowledge of UVM environments and classes /liliSome experience with main EDA vendors simulators such as Questasim and Xcelium /liliKnowledge of DFT structures and test pattern generation /liliSome experience in silicon validation / characterisation /liliExperience working on Git. /li /ulpFor more information, please contact Rob Hudson. /ppDigital Engineer • Parma, Emilia Romagna /p #J-18808-Ljbffr