PstrongPrincipal Physical Digital Design Engineerbr/strongstrongApply through LinkedInbr/strongstrongThe position in briefbr/strongstrongJob title: /strong Principal Physical Digital Design EngineerbrstrongWorkplace: /strongPavia/Bologna, ItalybrstrongDeadline: /strong brstrongHow to apply /strong: Apply through LinkedInbrstrongAbout Fondazione Chips-ITbr/strongThe Foundation “Italian Center for the Design of Semiconductor Integrated Circuits,” also known as the Chips-IT Foundation, is a nonprofit research and technology organization under the supervision of the Ministries of Industry.brThe Foundation is Italy’s first RTO (Research and Technology Organization) vertically focused on semiconductor research and stands as a center of excellence in frontier research on semiconductor design, as well as a pivotal center of the Italian semiconductor ecosystem and expertise.brstrongMissions Of The Foundationbr/strongullipromote the design and development of integrated circuits /lilistrengthen the system of professional training in the field of microelectronics /liliensure the establishment of a network of universities, research centers and enterprises that fosters innovation and technology transfer in the fieldbr/li /ulstrongRolebr/strongThe Chips-IT Foundation is expanding its microelectronics design team and is seeking a highly experienced Principal Physical Design Engineer to play a key technical leadership role in advanced System-on-Chic (SoC) development programs. The position will contribute to cutting-edge RD activities, working closely with architecture, RTL, verification, and technology teams in a state-of-the-art microelectronics design environment. The Principal Physical Design Engineer will be responsible for leading and executing complex digital design flows for advanced semiconductor nodes. The role requires deep hands-on expertise across the full physical implementation lifecycle, from netlist handoff through place route, signoff, and tape-out, while also providing technical mentorship and driving best practices within the design team.brThe work can be carried out either in Pavia or in Bologna.brstrongKey Responsibilitiesbr/strongulliLead and execute end-to-end physical design flows for complex SoCs and IP blocks, from RTL handoff to GDSII. /liliCollaborate closely with RTL, verification, DFT, and architecture teams to resolve design and implementation issues. /liliWork with PDKs and technology teams to ensure correct usage of advanced-node design rules and constraints. /liliDevelop, document, and improve physical design methodologies, scripts, and automation flows. /liliMentor junior engineers and provide technical leadership across physical design activities.br/li /ulstrongRequired Qualificationsbr/strongulliMaster’s degree (or PhD) in Electrical Engineering, Computer Engineering, or a related field. /liliExtensive hands-on experience in physical design for advanced technology nodes (e.g., 16nm and below). /liliStrong expertise with industry-standard EDA tools (Cadence, Synopsys, Siemens). /liliSolid understanding of semiconductor fabrication processes and foundry design requirements. /liliProficiency in Tcl, Python, or Perl for flow automation and methodology development. /liliExperience supporting multiple tape-outs in advanced nodes.br/li /ulstrongWhat We Offerbr/strongulliCompetitive compensation and contract type, to be negotiated based on qualifications and experience /liliPossibility to enter into a PhD conjugating your job with a research program that will grant you the PhD title. /liliLunch tickets /liliPrivate health care coverage depending on your role and contract /liliStructured growth path, with ongoing access to training and updates /liliNetworking opportunities with industry-leading professionals /liliInternational environment /liliHybrid work policy /liliTax deductions: Candidates from abroad, comprising Italian citizens, who have carried scientific research activity abroad and meet specific requirements, may be entitled to a taxable income deduction up to 90% for a period of 6 to 13 yearsbr/li /ulemNon verrà redatta e pubblicata alcuna graduatoria o elenco degli idonei.br/emstrongLa Fondazione Si Riserva La Facoltà Dibr/strongulliprorogare o riaprire il termine di scadenza del presente avviso; /lilirevocare il presente avviso; /lilinon procedere ad alcuna scelta tra le candidature presentate, ove ritenute non rispondenti alle funzioni di cui all’avviso; senza che gli interessati possano avanzare alcuna pretesa o diritto. /li /ul /p #J-18808-Ljbffr