Experteer OverviewJoin Marvell's CE-OPHY team to design high-speed analog blocks and complete IPs for optical transceivers used in data centers and telecom networks. You will own macro-level designs, mentor junior designers, and collaborate across functions to push performance and power efficiency in next-generation transceivers. This role places you at the core of submicron process design, tackling real-time data challenges at multi‐GHz speeds. You'll contribute to Marvell's reputation for market-leading optical PHY solutions in a fast‐paced, collaborative environment.Retribuzione / BenefitsAnalyze block specifications and select suitable topologiesDesign analog blocks at transistor levelSupervise layout activities, provide guidelines, and conduct post-layout verificationsModel blocks and validate modelsCollaborate with other teams to enhance existing solutionsTake responsibility for designing entire analog macros or IPsParticipate in cross‐functional meetings and interact with other functionsTrain and mentor junior designersResponsabilitàMaster's degree in Electrical Engineering or PhD in Electrical Engineering (microelectronics preferred) with 10+ years (Master) or 7+ years (PhD) of relevant experienceProven experience in independently designing ICs from architecture to lab characterization with full macro/IP ownershipStrong analog design skills, preferably in multi‐GHz rangeExtensive experience in analog custom layout supervisionFamiliarity with EDA CAD toolsExperience in IC performance measurement and correlating simulations with measurementsDirect project experience in multi‐Gbps electrical SerDes or electro‐optical transceivers or advanced CMOS nodes (FinFET) preferredStrong communication, presentation, and documentation skillsProficiency in Italian and English (min B2)Requisiti fondamentaliCompetitive compensationGreat benefitsCollaborative environmentInclusive cultureGrowth and development opportunities
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