PbJob Description /b /ppWe are seeking creative and hardworking engineers to join our outstanding Analog / Mixed-Signal Verification team. /ppYou will collaborate with systems and design teams to facilitate top-down design methodology. You will also work with chip and DV leads to plan, set up, and execute AMS / UVM verification. This position will play a vital role in streamlining development methodology for our organization. /ppbKey responsibilities: /b /polliProject setup: tools, versions, and technology /liliSet up and manage project environments and workspaces /liliMaintain PDK integrity and ensure flawless integration in project databases /liliDefine and own tape-out flows and tape-out quality assurance /liliBuild database structure with revision control system /liliDevelop scripts and automation tools to optimize design flows /liliAutomate verification with Python script command line and PyQt GUI /liliAutomate Cadence IC work with skill code scripts and GUI /liliSet up Virtuoso environment for mixed-signal verification /liliProvide first CAD contact support for the team /li /olpbAMS Verification: /b /polliValidate system feasibility and integrity with VerilogAMS or SystemVerilog models /liliAutomate top-level block connections with EDA skills and Python scripts /liliDevelop behavioral analog models (VerilogAMS / SystemVerilog) /liliSupport analog designers with model writing and promote best practices /liliPerform analog-focused mixed-signal verification /liliCreate and maintain verification plans, track progress, and analyze regression results /liliConduct analog/mixed-signal self-checking simulations /liliCollaborate with colleagues from analog and digital design and verification, as well as concept engineering /liliWork with multi-functional teams to streamline chip-level integration /liliContribute to verification planning and AMS simulation on full custom ASICs /liliDevelop test plans, test benches, and verification methodologies /liliSupport regression debugging and flow/infrastructure development /liliInterpret analog circuit schematics into abstract models /li /olpbQualifications: /b /polliMS or higher in Electrical Engineering /lili5+ years in CAD support or design flow development in microelectronics /liliStrong knowledge of Cadence tools and IC design methodologies /liliProficient in scripting (TCL, Shell, Python, etc.) /liliExperience with data management tools such as Git or Cliosoft /liliSolid understanding of the full IC design process /lili8+ years of analog design and verification experience /liliStrong background in analog integrated circuit design /liliExperience with SystemVerilog for RNM modeling, test bench development, and verification /liliHands-on experience in mixed-signal design /liliExcellent analytical and problem-solving skills /liliAbility to collaborate closely with digital/analog designers, engineers, and manufacturing teams /liliAbility to create, evaluate, debug, and improve verification processes /li /olpbAdditional Information: /b /ppRenesas is an embedded semiconductor solution provider committed to making lives easier. We offer scalable and comprehensive solutions across automotive, industrial, infrastructure, and IoT industries, with a broad product portfolio including high-performance computing, embedded processing, analog connectivity, and power. /ppWith over 21,000 professionals in more than 30 countries, we continue to expand our reach, designing sustainable, power-efficient solutions that help communities thrive. /ppbAt Renesas, you can: /b /pulliAdvance your career in technical and business roles across multiple product groups and functions /liliDevelop innovative products and solutions to meet global customer needs /liliWork in a flexible, inclusive environment that supports your performance and well-being /li /ulpAre you ready to own your success and make your mark? /ppbJoin Renesas. Let’s shape the future together. /b /ppRenesas Electronics is an equal opportunity employer committed to diversity and inclusion. For more information, see our Diversity Inclusion Statement. /p #J-18808-Ljbffr