FMC develops ferroelectric emerging Non-Volatile Memory solutions for stand-alone and embedded applications.
Having emerged as a dynamic spin-off from TU Dresden/NaMLab in 2016, we have progressed beyond the startup phase to solidify our position as a significant player in the Memory industry. We are pursuing the once-in-a-lifetime opportunity to establish a brand-new memory product in a market that is craving this innovation.
We are inviting you to be part of this exhilarating journey. As our DDR RTL engineer (m/f/d), you will be at our headquarter in Dresden or Milan office.
* Responsible for the design and verification of high-speed DDR control logic interface including command decode, address registers, mode registers, data path and clock tree
* Perform synthesis, timing and power analysis
* Optimize performance, power and area parameters
* Work closely with AMS, verification and layout teams
* Verify compliance with JEDEC specifications
Your profile:
* 8+ years of experience in high speed interface design
* DDR4 RTL design experience for memory or controller devices
* Familiarity with industry-standard design and simulation tools (e.g., VDI, Xcelium, Genus, Conformal)
Period: Planned starting date ASAP
Location: Milan (Italy) or Dresden (Germany)
We offer:
Benefits includes inspiring work environment, flat hierarchies, opportunity for personal and professional growth (including complimentary training opportunities), multi-cultural team, regular team events, Urban Sports Club membership, free public transportation ticket or fuel voucher, lunch allowance and a competitive salary in a semiconductor environment.
For further questions or to apply please contact:
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