H3Senior FPGA Design and Verification Engineer /h3h3JMA Wireless /h3h3Specialista Senior / Project Manager /h3pBologna /ppEngineering Technology – 5G Digital Design / /ppFull-Time / /ppOn-site /ppJMA makes 5G possible for organizations with the most critical connectivity demands in the world. From its global tech centers, JMA is ushering in a new era of connectivity for leading mobile carriers, the most iconic stadiums, major universities, leading healthcare facilities, and the busiest transit centers. /pp5G is more than another G on your phone — it is a generational opportunity to change the way the world operates. Join the industry’s fastest growing technology company to shape that future today. /ppThe Senior FPGA Engineer will play a key role in the design, implementation, and optimization of FPGA-based solutions for JMA projects. Contribute to the development of innovative products, collaborate with cross-functional teams, including HW design, QA, and Operations, and lead FPGA design efforts from conception to delivery. This position will work onsite at the JMA office in Castel San Pietro Terme (BO). /ph3Responsibilities: /h3ullibFPGA Design and Development: /b /liliArchitect and design FPGA-based systems to meet project requirements. /liliImplement and optimize FPGA designs for performance, power, and area efficiency. /liliCollaborate with hardware and software teams to integrate FPGA solutions into larger systems. /lilibVerification and Testing: /b /liliDevelop and execute comprehensive test plans to ensure the reliability and functionality of FPGA designs. /liliDebug and troubleshoot FPGA designs, identifying and resolving issues in a timely manner. /lilibDocumentation: /b /liliGenerate clear and comprehensive documentation for FPGA designs, including specifications, test plans, and user guides. /liliMaintain version-controlled design documentation throughout the development lifecycle. /liliProvide mentorship and guidance to junior FPGA engineers. /liliCollaborate with cross-functional teams to ensure seamless integration of FPGA solutions. /lilibResearch and Innovation: /b /liliStay abreast of industry trends and emerging technologies in FPGA design. /liliExplore and recommend new tools, methodologies, and techniques to enhance FPGA development processes. /lilibProject Management: /b /liliWork closely with project managers to define project milestones, deliverables, and timelines. /liliContribute to project planning and resource allocation for FPGA development activities. /li /ulh3Qualifications /h3ullibExperience: /b /liliMinimum of 6 years of hands-on experience in FPGA design and development. /liliExperience in the FPGA based 5G Wireless systems and/or ORAN Fronthaul technology will represent a plus. /liliProven track record of successfully delivering complex FPGA projects from concept to production. /lilibTechnical Skills: /b /liliStrong understanding of high-speed digital design and signal integrity principles. /liliExpertise of RTL optimized design technique in digital and DSP domain with Verilog/SystemVerilog and/or VHDL. /liliProficient in using FPGA design-verification tools from vendors such as Xilinx/AMD or Altera/Intel, simulator Questasim. /liliKnowledge of FPGA’s synthesis, place-n-route process, and optimization for timing closure techniques. /liliFamiliar with FPGA interfaces – 10/25/100GbEth, ADC/DAC, uART, SPI, I2C, DDR4, JESD204B, PCIe. /liliAbility to write module-level and/or top-level FPGA testbench with testcases to ensure the design coverage in simulation. /liliLab troubleshooting skills - mastering the lab set up, equipment and leveraging FPGA’s chipscope (or signaltap) debug tool. /liliKnowledge of at least one between bash and Python scripting language. /liliProficiency with C programming language. /liliSkills that are not mandatory but that will be considered a plus /liliProficiency with Linux systems, both as development environments and as FGPA embedded OS. This is a very strong plus. /liliOther languages considered a plus are tcl, Makefile. /liliFamiliarity with bitbucket, Jira-based workflow is a plus. /liliFamiliarity with Jenkins framework and groovy language is a plus. /liliKnowledge of FPGA security embedded systems, including ORAN Fronthaul’s vulnerability security WG11, secure boot, and MACsec. /li /ul#LI-AC1pAt JMA, we don’t just accept differences — we embrace them. JMA is proud to be an equal opportunity workplace. We do not discriminate based upon race, religion, color, national origin, gender (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristic. /p #J-18808-Ljbffr