Ph3Job Summary /h3 pWe are seeking an experienced Senior DFT Designer to contribute to the development of cutting-edge mixed-signal and digital integrated circuits. This role involves responsibility for designing, implementing, and verifying DFT architectures for complex SoCs working closely with RTL, physical design, verification, product and test teams to ensure robust testability and high-quality silicon. /p h3Job Responsibilities /h3 ul liLead and execute the full DFT design flow, including specification definition, architectural design, RTL coding (Verilog/SystemVerilog), synthesis, static timing analysis (STA), verification. /li liDevelop and integrate scan insertion, test compression, and ATPG patterns. /li liImplement memory BIST strategies. /li liCollaborate closely with digital, analog, mixed-signal, product, test and software teams. /li liCollaborate with RTL and physical design teams for DFT insertion and timing closure. /li liDevelop and implement innovative DFT architectures and design methodologies to meet challenging performance, power, area and quality targets. /li liOptimize test coverage, pattern count and test time. /li liPerform comprehensive DFT verification at RTL and gate level. /li liWork with ATE teams for test program development and silicon bring-up. /li liParticipate in post-silicon validation and debug activities, identifying and resolving issues to ensure product quality. /li liMentor junior engineers, provide technical guidance, and contribute to continuous improvement of DFT design processes and methodologies. /li liGenerate detailed design documentation, including specifications, test plans, and design reviews. /li liStay abreast of industry trends, emerging technologies, and best practices in digital IC design. /li /ul h3Requirements /h3 ul liBachelor or master degree in microelectronics, electronic engineering or related. /li liStrong expertise in DFT methodologies: Scan, MBIST, LBIST, JTAG. /li liHands‑on experience with industry standard ATPG tools. /li liProficiency in UPF/CPF‑based low‑power DFT. /li liKnowledge of fault models (stuck‑at, transition, path delay). /li liFamiliarity with physical design constraints for DFT. /li liExperience in silicon debug and ATE bring‑up. /li liKnowledge of Verilog, SystemVerilog, VHDL. /li liStrong commitment to schedule and work quality, good team player. /li liGood English capabilities. /li /ul /p #J-18808-Ljbffr