Ph3Job Summary /h3pWe are seeking an experienced Senior DFT Designer to contribute to the development of cutting‑edge mixed‑signal and digital integrated circuits. This role involves responsibility for designing, implementing, and verifying DFT architectures for complex SoCs working closely with RTL, physical design, verification, product, and test teams to ensure robust testability and high‑quality silicon. /ph3Responsibilities /h3ulliLead and execute the full DFT design flow, including specification definition, architectural design, RTL coding (Verilog/SystemVerilog), synthesis, static timing analysis (STA), and verification. /liliDevelop and integrate scan insertion, test compression, and ATPG patterns. /liliImplement memory BIST strategies. /liliCollaborate closely with digital, analog, mixed‑signal, product, test and software teams. /liliCollaborate with RTL and physical design teams for DFT insertion and timing closure. /liliDevelop and implement innovative DFT architectures and design methodologies to meet challenging performance, power, area and quality targets. /liliOptimize test coverage, pattern count and test time. /liliPerform comprehensive DFT verification at RTL and gate level. /liliWork with ATE teams for test program development and silicon bring‑up. /liliParticipate in post‑silicon validation and debug activities, identifying and resolving issues to ensure product quality. /liliMentor junior engineers, provide technical guidance, and contribute to continuous improvement of DFT design processes and methodologies. /liliGenerate detailed design documentation, including specifications, test plans, and design reviews. /liliStay abreast of industry trends, emerging technologies, and best practices in digital IC design. /li /ulh3Requirements /h3ulliBachelor or master degree in microelectronics, electronic engineering or related field. /liliStrong expertise in DFT methodologies: Scan, MBIST, LBIST, JTAG. /liliHands‑on experience with industry‑standard ATPG tools. /liliProficiency in UPF/CPF‑based low‑power DFT. /liliKnowledge of fault models (stuck‑at, transition, path delay). /liliFamiliarity with physical design constraints for DFT. /liliExperience in silicon debug and ATE bring‑up. /liliKnowledge of Verilog, SystemVerilog, VHDL. /liliStrong commitment to schedule and work quality, good team player. /liliGood English capabilities. /li /ul /p #J-18808-Ljbffr