Ph3Senior Digital IC Designer /h3 pCompany: NXP Semiconductors Netherlands B.V. Branch Office Italia /p h3Job Summary /h3 pWe are seeking an experienced Senior Digital IC Designer to contribute to the development of cutting‑edge mixed-signal and digital integrated circuits. This role involves leading complex design tasks from concept to silicon, ensuring high‑performance and reliable solutions for NXP's advanced semiconductor products. /p h3Job Responsibilities /h3 ul liLead and execute the full digital IC design flow, including specification definition, architectural design, RTL coding (Verilog/SystemVerilog), synthesis, static timing analysis (STA), formal verification, and power analysis. /li liCollaborate closely with analog, mixed‑signal, and software teams to define interfaces, optimize system performance, and ensure seamless integration. /li liDevelop and implement innovative digital architectures and design methodologies to meet challenging performance, power, and area targets. /li liPerform comprehensive design verification using simulation tools, formal verification techniques, and hardware emulation. /li liParticipate in post‑silicon validation and debug activities, identifying and resolving issues to ensure product quality. /li liMentor junior engineers, provide technical guidance, and contribute to continuous improvement of design processes and methodologies. /li liGenerate detailed design documentation, including specifications, test plans, and design reviews. /li liStay abreast of industry trends, emerging technologies, and best practices in digital IC design. /li /ul h3Job Qualifications /h3 ul liMaster's degree or Ph.D. in Electrical Engineering, Electronics Engineering, or a related field. /li liMinimum of 7+ years of experience in digital IC design, with a strong portfolio of successfully completed projects. /li liExpertise in Verilog/SystemVerilog for RTL design and verification. /li liProven experience with industry‑standard EDA tools for synthesis, STA (e.g., Synopsys Design Compiler, Cadence Genus, Primetime), formal verification (e.g., Synopsys Formality), and simulation (e.g., VCS, QuestaSim). /li liStrong understanding of digital design principles, clock domain crossing (CDC) issues, power integrity, and low‑power design techniques. /li liExperience with scripting languages (e.g., Python, Perl, Tcl) for automation and design flow optimization. /li liFamiliarity with mixed‑signal integration challenges and verification methodologies. /li liExcellent problem‑solving, analytical, and debugging skills. /li liStrong communication and interpersonal skills, with the ability to work effectively in a collaborative team environment. /li liAbility to take initiative, work independently, and lead technical discussions. /li /ul /p #J-18808-Ljbffr